How To Index A Register Bit In Systemverilog

In my last commodity on plain old Verilog Arrays, I discussed their very express feature set. In comparison, SystemVerilog arrays have greatly expanded capabilities both for writing synthesizable RTL, and for writing non-synthesizable examination benches. In this commodity, we'll take a look at the synthesizable features of SystemVerilog Arrays nosotros can use when writing design RTL.

Packed vs Unpacked SystemVerilog Arrays

Verilog had simply one type of array. SystemVerilog arrays can be either packed or unpacked. Packed assortment refers to dimensions alleged afterwards the type and before the information identifier name. Unpacked array refers to the dimensions declared subsequently the information identifier name.

bit [7:0] c1;         // packed array of scalar scrap real      u [seven:0];    // unpacked array of real  int Assortment[0:vii][0:31]; // unpacked array declaration using ranges int Array[8][32];     // unpacked array annunciation using sizes

Packed Arrays

A ane-dimensional packed assortment is as well chosen a vector. Packed assortment divides a vector into subfields, which tin be accessed as array elements. A packed array is guaranteed to exist represented equally a contiguous fix of bits in simulation and synthesis.

Packed arrays can be made of merely the unmarried flake data types (bit, logic, reg), enumerated types, and other packed arrays and packed structures. This too means you cannot have packed arrays of integer types with predefined widths (e.thousand. a packed array of byte).

Unpacked arrays

Unpacked arrays can be fabricated of any data type. Each fixed-size dimension is represented by an address range, such as [0:1023], or a single positive number to specify the size of a fixed-size unpacked array, such as [1024]. The notation [size] is equivalent to [0:size-1].

Indexing and Slicing SystemVerilog Arrays

Verilog arrays could simply be accessed one element at a time. In SystemVerilog arrays, you can also select one or more contiguous elements of an array. This is called a slice. An array piece tin can only apply to 1 dimension; other dimensions must accept single index values in an expression.

Multidimensional Arrays

Multidimensional arrays can be declared with both packed and unpacked dimensions. Creating a multidimensional packed array is analogous to slicing up a continuous vector into multiple dimensions.

When an array has multiple dimensions that can be logically grouped, it is a skillful idea to use typedef to ascertain the multidimensional array in stages to heighten readability. But find the order of the dimensions get a little confusing.

chip [3:0] [7:0] joe [0:9] // 10 elements of four viii-bit bytes                           // (each element packed into 32 bits)  typedef chip [four:0] bsix;   // multiple packed dimensions with typedef bsix [nine:0] v5;            // equivalent to bit[9:0][4:0] v5 - thanks Yunsung!  typedef bsix mem_type [0:three]; // array of four unpacked 'bsix' elements mem_type ba [0:7];           // array of eight unpacked 'mem_type' elements                              // equivalent to bit[4:0] ba [0:seven][0:3] - thanks Yunsung!

SystemVerilog Array Operations

SystemVerilog arrays support many more operations than their traditional Verilog counterparts.

+: and -: Annotation

When accessing a range of indices (a slice) of a SystemVerilog array, you tin can specify a variable slice past using the [start+:increment width] and [outset-:decrement width] notations. They are simpler than needing to calculate the verbal offset and end indices when selecting a variable slice. The increment/decrement width must be a constant.

bit signed [31:0] busA [seven:0]; // unpacked array of viii 32-bit vectors int busB [1:0];               // unpacked array of 2 integers busB = busA[7:half dozen];             // select a 2-vector slice from busA busB = busA[half dozen+:2];            // equivalent to busA[vii:6]; typo fixed, cheers Tomer!

Assignments, Copying, and other Operations

SystemVerilog arrays support many more than operations than Verilog arrays. The post-obit operations can be performed on both packed and unpacked arrays.

A       = B;       // reading and writing the array A[i:j]  = B[i:j];  // reading and writing a slice of the array A[ten+:c] = B[y+:d]; // reading and writing a variable slice of the array A[i]    = B[i];    // accessing an element of the array A       == B;      // equality operations on the array A[i:j]  != B[i:j]; // equality operations on slice of the array

Packed Array Assignment

A SystemVerilog packed array tin be assigned at in one case like a multi-flake vector, or also as an private element or slice, and more.

logic [1:0][1:0][vii:0] packed_3d_array;  always_ff @(posedge clk, negedge rst_n)   if (!rst_n) begin     packed_3d_array <= '0;      // assign 0 to all elements of array   end   else begin     packed_3d_array[0][0][0]   <= 1'b0;         // assign one flake     packed_3d_array[0][0]      <= 8'h0a;        // assign i element     packed_3d_array[0][0][3:0] <= 4'ha;         // assign role select     packed_3d_array[0]         <= 16'habcd;     // assign slice     packed_3d_array            <= 32'h01234567; // assign entire array every bit vector   end

Unpacked Array Assignment

All or multiple elements of a SystemVerilog unpacked array tin be assigned at once to a listing of values. The listing tin contain values for individual assortment elements, or a default value for the entire array.

logic [7:0] a, b, c; logic [7:0] d_array[0:3]; logic [seven:0] e_array[3:0]; // note index of unpacked dimension is reversed                           // personally, I prefer this form logic [seven:0] mult_array_a[three:0][3:0]; logic [7:0] mult_array_b[3:0][3:0];  always_ff @(posedge clk, negedge rst_n)   if (!rst_n) brainstorm     d_array <= '{default:0};      // assign 0 to all elements of assortment   finish   else brainstorm     d_array        <= '{8'h00, c, b, a}; // d_array[0]=8'h00, d_array[1]=c, d_array[2]=b, d_array[three]=a     e_array        <= '{8'h00, c, b, a}; // e_array[three]=8'h00, e_array[two]=c, e_array[1]=b, d_array[0]=a     mult_array_a   <= '{'{viii'h00, 8'h01, 8'h02, 8'h03},                         '{8'h04, eight'h05, 8'h06, viii'h07},                         '{8'h08, 8'h09, 8'h0a, 8'h0b},                         '{viii'h0c, eight'h0d, 8'h0e, eight'h0f}}; // assign to total array     mult_array_b[3] <= '{8'h00, eight'h01, viii'h02, 8'h03}; // assign to slice of array   stop

Determination

This article described the two new types of SystemVerilog arrays—packed and unpacked—also as the many new features that can exist used to manipulate SystemVerilog arrays. The features described in this article are all synthesizable, so you tin safely use them in SystemVerilog based RTL designs to simplify coding. In the side by side part of the SystemVerilog arrays article, I will hash out more usages of SystemVerilog arrays that can brand your SystemVerilog design lawmaking even more efficient. Stay tuned!

Resource

Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is but for Verification
1888-2012 IEEE Standard for SystemVerilog
SystemVerilog for Design Second Edition:
A Guide to Using SystemVerilog for Hardware Pattern and Modeling

Sample Source Code

The accompany source code for this commodity is a toy example module and testbench that illustrates SystemVerilog array capabilities, including using an array equally a port, assigning multi-dimensional arrays, and assigning slices of arrays. Download and run information technology to see how it works!

Download Article Companion Source Code

Go the Gratis, EXECUTABLE test demote and source lawmaking for this article, notification of new articles, and more!

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Jason has fourteen years' feel in the semiconductor industry, designing and verifying Solid Land Drive controller SoC. His areas of workinclude microarchitecture and RTL blueprint, dynamic and formal verification using UVM and Cadence JasperGold, and full-bit low power verification with UPF. Thoughts and opinions expressed in articles are personal and do not reflect that of Intel Corporation in whatever style.